In the field of integrated circuit (IC) modeling and fabrication, it is desirable to have an accurate estimate of yield for manufacturing a given IC model. Manufacturing variability is typically provided by foundries in the form of ascertained statistical variation factors (e.g., random variables) associated with specific circuit components. Numerous applications exist to model an IC performance based on the random variables provided by the foundries. Some applications make use of statistical techniques for sampling multiple random variables including Monte Carlo (MC) simulations to determine circuit performance. However, many available applications lack judicious sampling discrimination, resulting in lengthy and cost-ineffective use of computational capabilities. Further, lengthy simulation computations overly extend the turn-around time for modeling and re-modeling certain circuit components, creating a design bottleneck that manufacturers would desirably avoid.
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